Peculiarities of Forming of Microwave Arsenide-Gallium Submicron Structures of Large-scale Integrated Circuit

The peculiarities of technological processes of formation of submicron Schottky field transistors using arsenide-gallium technology, i.e. the technology of Schottky field transistors formation with a self-alifned gate on the basis of nitride or silicide of tungsten, are considered in the paper. A highly effective technology for the formation of capsular layers of AlN and BN nitride films by high-frequency magnetron sputtering of the proper target in nitric plasma for the realization of GaAs-based MOS-transistors is developed.


Introduction
Today Schottky field transistors (SFTs) are the main active elements of GaAs chips of the microwave range. The main purpose of their development is to increase the speed. Digital GaAs integrated circuits/large-scale integrated circuits (ICs/LSICs) belong to the class of ultra-high-speed ones, while analogue devices are generally designed to operate in the microwave range. The following advantages of GaAs compared to mono-Si are used in the development of SFTs and chips on their basis: higher electron mobility in weak electric fields and saturation velocities in strong fields; greater band gap widths and, consequently, a much higher specific resistance of unalloyed gallium arsenide, which allows to form semi-insulating (local and interlayer) layers in the LSIC-structures. However, GaAs is inferior to mono-Si for a number of parameters that are important for the formation of chips. In particular, the high density of surface states in MOS-structures of gallium arsenide does not allow it to form high-quality MOS-transistors and chips, low mobility of holes and small charge time of current carriers makes it difficult to develop bipolar complementary transistors. In this regard, the optimal active element, which allows to realize the advantages of GaAs in the IC/LSIC-structures, compared to mono-Si, is the field-effect transistor with the metal-semiconductor barrier.

I. Peculiarities of technology forming of SFT-structure
One of the first technologies for the formation of structures of arsenide-gallium SPTs is shown on Fig. 1.
The transistor is formed on the substrate 1 of the negative gallium arsenide, which has a slightly degenerate conductivity of p-type. To reduce it, when GaAs single crystals are grown by Czochralskiy method, chromium atoms are introduced in small amounts, which compensate the acceptors action. GaAs substrates made from such monocrystalline ingot have an increased static resistance and are called semi-insulating ones.
A highly doped n + -type source-drain regions 2 and more thin layer of n-type channel 3 are formed near the substrate surface 1 by the ion-doping method. The typical thickness of the layer 3 d 0 = 0.1-0.2 μm, and the concentration of donors in the channel N dc = (1-2)·10 17 сm -3 . Ions of silicon (Si + ), selenium (Se + ), and sulfur (S + ) are usually used as doping donor admixtures. Metallic electrodes of gate 4 (for example, in the form of Ti-W alloy) are deposited on the substrate surface above the layer 3. Metallic electrodes 5, for which the goldgermanium composition (AuGe-12) is used, provide contacts to source and drain. A dielectric layer 6 (SiO 2 ) is deposited on the surface of the substrate that is not in use. The metal gate electrode forms with a layer 3 a rectifying contact (the Schottky barrier), the typical equilibrium height of which is φ b = 0.7-0.8 V. The conductive channel between the source and drain is placed in layer 3. It is limited to the top of the depleted region 7 of Schottky barrier and from the bottomsubstrate 1. The thickness of the conductive channel is equal to the thickness of the depleted region 7. Typical source-drain distance L = 1.3 µm, the gate length is 0.5-1 µm. The operation principle of SFT is as follows.
The control voltage U gs is applied between the gate and the source, and on the drain -the positive one U ds is applied to drain. When the control voltage changes, the thickness of the depleted layer 7 L dep (U gs ), the thickness of the conductive channel d c (U gs ) = L dep (U gs ), its conductivity and the drain current changes too. If the gate voltage is equal to the threshold one U T , then the depth of the depleted layer 7 reaches the insulating substrate 1 (the channel thickness and the drain current are equal to zero). Threshold voltage is determined from the condition For normally open SFT the control voltage of the gate, at which the drain current flows, can vary from negative voltages (-2.5 V) to positive ones (+0.6 V). This voltage can be increased to +2.0 V by multi-charge combined implantation of light and heavy ions. There is a current in gate circle at high positive voltages at the gate (more than 2.5 V), since the barrier metalsemiconductor opens. Therefore, this barrier is also advisable to increase to a value of 1-1.2 V. As a result, the drain current is limited by the value of I d max1 , which corresponds to the gate voltage U gs max . For normally closed transistors the gate voltage, at which the drain current flows, is positive and can vary within 0-1.6 V. Here, the maximum drain current should be limited to the value of I d max2 . Therefore, I d max1 >> I d max2 for SPTs with the same channel size (0.8-1.2 μm).
Normally closed SFTs are the most promising for GaAs. It is necessary to ensure that the threshold voltage dispersion is as low as possible at forming such transistors. Reducing such threshold voltage dispersion presents today a serious technological problem for multicharge retrograde ion implantation, since this voltage is linearly or quasilinearly depends on the concentration of donors in the channel and quadratically on the layer thickness.
Both normally open and normally closed SFTs are  where b -channel width, L 0 -effective channel length. Thanks to the higher mobility of electrons (4-5·10 3 сm 2 /V·s) the steepness value is much higher than in silicon MOS-transistors at the same size. Unlike mono-silicon, gallium arsenide is characterized by a lower critical electric field strength (3·10 3 V/сm), at which the drift velocity reaches its saturation. Therefore, the effect of strong field appears at a greater channel length and drain voltage in GaAs SFT, than in silicon one. Table 1 shows for comparison the basic electrophysical parameters of GaAs and Si at T = 300 K. In transistors with a short channel (L < 0.8 μm), the drift velocity reaches saturation, the drain-gate characteristic is close to the linear one, and the steepness depends weakly on the gate voltage and is determined by the expression: 00 nsat Sdd εε = . Thus, the greater steepness of GaAs SFT compared to silicon MOS-transistors of the same size is due to a higher saturation velocity of 2·10 7 сm/s.
Unlike silicon MOS-transistors with induced channel, GaAs SFT have very small parasitic gate-source and gate-drain capacities since the gate does not overlap region 2. In addition, there are drain-substrate and source-substrate barrier capacities, since the substrate is semi-insulating -the concentration of admixtures is Maximum resistivity of non-doped material, Оhm·сm 10 7 -10 9 10 5 4 Lifetime of of minority charge carriers, s 10 -5 10 -3 5 Density of surface states of MOS-structures, сm -2 10 12 -10 13 10 10 -10 11 CbLL εε = , which is the barrier capacitance of the metal-semiconductor contact transition, has a significant value. At the voltage U gs > U T it is calculated by the above formula. To reduce this capacity, it is necessary to reduce the length of the channel (L < 0,6 μm), which increases the SFT speed [2].
The limit frequency of steepness is determined by the transit time t tr of the of electrons through the channel at a small length of the gate channel trgeff tL υ = , i.e. When SFT is worked in pulsed mode, its switching time is determined by the transit time of electrons through the channel and the recharge time of the loading capacity. Increasing of speed of GaAs digital chips compared to silicon ones is due to an increase in the steepness of SFT, as well as a decrease in the transit time of the electrons and parasitic capacitors of the transistors. Therefore, to increase the steepness of SFT, a selfaligned technology with a gate was developed. Table 2 shows typical electrophysical parameters of the test structure of SFT with the structure depicted on Fig. 1.
Consider the structure of SFT with self-aligned gate, the main technological processes of which are shown at Fig. 3.
The SFT-structure is formed on a semi-insulating GaAs substrate, where n-layer of 0.08-0.1 µm in thickness is formed by selective ionic doping of substrate with silicon (Si ++ ) through SiO 2 mask. The SFT channel is located in this layer, on the surface of which the gate is formed. The gate of the transistor represents a strip of tungsten silicon of 0.8 µm in length. Tungsten silicon is chosen as a gate to withstand a photonic treatment at 700°C for resistance reducing.
Selective epitaxial growth by vapour-chemical reactions from metal-organic compounds or molecularbeam epitaxy is used at the formation of n + -type drainsource regions. Then, a dielectric SiO 2 layer is deposited and photonic annealing is carried out to activate and reduce radiation defect, which leads to a significant increase in the mobility of charge carriers. Plasmachemical etching opens the windows for the contacts in the insulator and the contacts to the drain-source regions are formed by deposition a metal layer from AlGe-12 alloy using ion milling [3].
The following electrophysical parameters were obtained for SFT with self-aligned gate at L g =1.5μm and b = 1 mm: U T = 0.6 V, R load = 0.75 Ohm, S/b = 87 mS/mm. Compared to SFT formed without selfaligning of the same size, the source resistance decreased by 5-8 times, and the steepness increased by 3-5 times. In a structure with a self-aligned gate, the breakdown voltage at the gate is determined by the concentration of admixtures in the n + -regions, as they adhere to the gate.
The maximum donor concentration in n + -regions is 7·10 17 ÷ 1·10 18 сm -3 and the breakdown voltage of the gate is 6-10 V at ion energy 150 eV and dose (1.7-2)·10 13 сm -2 . The disadvantage of such a structure with a self-aligned gate is a slightly increased parasitic gatesource and gate-drain capacitances, which can be reduced by using high-resolution lithography [4].